The present invention relates to a semiconductor device and more specifically to a semiconductor device that performs an arithmetic operation on multiple data in a parallel manner using multiple processors each for performing an arithmetic operation on data.
In recent years, in semiconductor devices such as a processor, it is commonly practiced that multiple processor elements are installed, a data processing is performed by the multiple processor elements in parallel, and thereby processing performance is improved. Especially, a processor for performing an operation by a single operation instruction on the multiple data among processors having the multiple processor elements is called an SIMD (Single Instruction Multi Data) type processor. Since such an SIMD type processor can perform arithmetic operations at high speed by being used for an image processing in which the same operation is performed on multiple pieces of pixel data, it is useful.
Examples of such a processor are disclosed in Japanese Unexamined Patent Publication No. Hei4 (1992)-295953, Japanese Unexamined Patent Publication No. 2009-123074, Japanese Unexamined Patent Publication No. 2007-73010, and “An integrated memory array processor architecture for embedded image recognition systems”, ISCA2005, kyo. S. In Japanese Unexamined Patent Publication No. Hei4 (1992)-295953, Japanese Unexamined Patent Publication No. 2009-123074, Japanese Unexamined Patent Publication No. 2007-73010, and “An integrated memory array processor architecture for embedded image recognition systems”, ISCA2005, kyo. S, the multiple processor elements perform a parallel data processing. At this time, in Japanese Unexamined Patent Publication No. Hei4 (1992)-295953, Japanese Unexamined Patent Publication No. 2009-123074, Japanese Unexamined Patent Publication No. 2007-73010, and “An integrated memory array processor architecture for embedded image recognition systems”, ISCA2005, kyo. S, devices (or processors) each have a data transfer network through which data transfer is performed among the processor elements. Moreover, Japanese Unexamined Patent Publication No. Hei4 (1992)-295953, Japanese Unexamined Patent Publication No. 2009-123074, Japanese Unexamined Patent Publication No. 2007-73010, and “An integrated memory array processor architecture for embedded image recognition systems”, ISCA2005, kyo. S can each improve a speed of the data transfer between the processor elements by having the data transfer network. In the image processing, there are many processings each of which needs to transfer image information between the processor elements in a movement processing of an image in vertical direction and horizontal direction, a rotation processing of an image, a filter processing, etc., and therefore an effect of improvement in throughput achieved by having the data transfer network is large.